`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:27:09 07/08/2015 
// Design Name: 
// Module Name:    LatchIDEX 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LatchIDEX(
	input RegDstIn, 
	input RegWriteOIn,
	input ALUSrcIn, 
	input PCSrcIn,
	input MemReadIn,
	input [3:0] MemWriteIn,
	input MemToRegIn,
	input [1:0] ALUOpIn, 
	input [2:0] LoadOpIn, 
	input [1:0] StoreOpIn, 
	input [2:0] InmCtrlIn,
	input [31:0] E2AdderIn,
	input [31:0] ReadData1In,
	input [31:0] ReadData2In,
	input [31:0] ExtSigIn,
	input [4:0] RTIn,
	input [4:0] RDIn,
	input [4:0] RSIn,
	input jmpIn,
	input yamp,
	input vranch,
	input stallone,
	input clk,
	output reg jmpOut,
	output reg RegDstOut, 
	output reg RegWriteOOut,
	output reg ALUSrcOut, 
	output reg PCSrcOut,
	output reg MemReadOut,
	output reg [3:0] MemWriteOut,
	output reg MemToRegOut,
	output reg [1:0] ALUOpOut, 
	output reg [2:0] LoadOpOut, 
	output reg [1:0] StoreOpOut, 
	output reg [2:0] InmCtrlOut,
	output reg [31:0] E2AdderOut,
	output reg [31:0] ReadData1Out,
	output reg [31:0] ReadData2Out,
	output reg [31:0] ExtSigOut,
	output reg [4:0] RTOut,
	output reg [4:0] RDOut,
	output reg [4:0] RSOut
    );

always@(negedge clk) begin
	if(yamp || vranch || stallone) begin
		RegDstOut = RegDstIn;
		RegWriteOOut = 0;
		ALUSrcOut = ALUSrcIn;
		PCSrcOut = 0;
		MemReadOut = MemReadIn;
		MemWriteOut = 0;
		MemToRegOut = MemToRegIn ;
		ALUOpOut = ALUOpIn; 
		LoadOpOut = LoadOpIn;
		StoreOpOut = StoreOpIn; 
		InmCtrlOut = InmCtrlIn;
		E2AdderOut = E2AdderIn;
		ReadData1Out = ReadData1In;
		ReadData2Out = ReadData2In;
		ExtSigOut = ExtSigIn;
		RTOut = RTIn;
		RDOut = RDIn;
		RSOut = RSIn;
		jmpOut = jmpIn;
	end
	else begin
		RegDstOut = RegDstIn;
		RegWriteOOut = RegWriteOIn;
		ALUSrcOut = ALUSrcIn;
		PCSrcOut = PCSrcIn;
		MemReadOut = MemReadIn;
		MemWriteOut = MemWriteIn;
		MemToRegOut = MemToRegIn ;
		ALUOpOut = ALUOpIn; 
		LoadOpOut = LoadOpIn;
		StoreOpOut = StoreOpIn; 
		InmCtrlOut = InmCtrlIn;
		E2AdderOut = E2AdderIn;
		ReadData1Out = ReadData1In;
		ReadData2Out = ReadData2In;
		ExtSigOut = ExtSigIn;
		RTOut = RTIn;
		RDOut = RDIn;
		RSOut = RSIn;
		jmpOut = jmpIn;
	end
end

endmodule
